1. Field of the Invention
The present invention is directed to the field of reliability testing of semiconductor devices with layered structures. In particular, the present invention is directed to an in situ reliability test for semiconductor devices with a layered structure under direct current bias.
2. Description of the Related Technology
One common device with a layered structure is a semiconductor transistor, one type of which is a high electron mobility transistor (HEMT). HEMTs are used as signal amplifiers, at microwave and millimeter wave frequencies, in a wide range of applications. HEMTs may be implemented as discrete transistors or in integrated circuits. Microwave monolithic integrated circuits with HEMTs are used in space, military and commercial applications, such as satellite transceivers, global positioning system (GPS)-based navigation systems, broadband wireless networking systems, and radar.
Unlike conventional semiconductor transistors, HEMTs are field effect transistors comprising an electron layer at the interface between two different semiconductor materials having different band gaps. There are multiple types of HEMTs. AlGaAs/GaAs based HEMTs as the most common type. A new type of HEMT is one that is based on an AlGaN/GaN heterostructure. This type of HEMT provides several advantages such as a wide band gap, a superior carrier saturation velocity, thermal conductivity, and a high breakdown field, all of which are useful for high temperature and high speed applications.
AlGaN/GaN based HEMTs can be operated at high voltages, of up to 42 volts, through three electrodes: source, gate and drain. The ability of HEMTs to function at higher voltages reduces power consumption and decreases their reliance on a cooling system. Consequently, AlGaN/GaN based HEMTs can reduce the operational costs of high power microwave transmitters, especially since maintaining a cooling system may contribute a significant fraction of the operational cost of many of these applications. A schematic diagram of a typical AlGaN/GaN based HEMT is shown in FIG. 1. The dotted line represents a two-dimensional electron gas (2DEG) interfacial region in Ga-polar HEMTs, which is between the AlGaN and GaN layers.
Even with their many advantages, AlGaN/GaN based HEMTs have a tendency to fail when high voltages are supplied to the HEMTs under certain stressful operational conditions. Failure modes of AlGaN/GaN based HEMTs are not well understood, though it is believed that an inverse piezoelectric effect may be a mechanism that causes failures in these HEMTs. Particularly, when AlGaN/GaN based HEMTs are operated at a high voltage, a large electric field is generated under the drain edge of the gate, which results in localized mechanical stresses concentrated in the AlGaN barrier. These high stresses are graphically illustrated in FIG. 2 by the arrows.
FIG. 2 further shows a two-dimensional electron gas (2DEG), a high mobility electron layer formed below the junction of AlGaN layer and a GaN layer. Additionally, due to their lattice mismatch, the AlGaN/GaN interface is already under substantial tensile strain at a “rest” state, or when it is not under an applied voltage. When under electrical stress, the elastic energy in this high-field gate edge region causes added strain. Defects act as pathways for gate leakage currents, which results in electron trapping and degradation of the transport properties of the electron channel underneath.
Currently, a common approach to study failures of HEMTs is by observing their surface morphology with surface imaging techniques, such as by use of cathodoluminescence spectroscopy, atomic force microscopy, or transmission electron microscopy. For example, Makaram et al. in an article entitled “Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors,”Applied Physics Letters, vol. 96, 233509-1 to 233509-3, (2010), discusses an investigation of surface morphology of electrically stressed AlGaN/GaN HEMTs using atomic force microscopy and scanning electron microscopy. Before imaging, the stressed HEMTs were subjected to several time-consuming preparation steps, including removing the SiN passivation layer by chemical etching; removing contact and gate metals using aqua regia (3:1 HCl:HNO3) at 80° C. for 20 minutes; and cleaning the surface using piranha solution (H2SO4:H2O) for 5 minutes at 15° C. Also, these imaging based techniques only reveal surface morphology, but not the internal microstructural changes of the HEMTs.
U.S. Pat. No. 7,411,226 (“the '226 patent”) discusses a high electron mobility transistor structure with a gate metal stack including an additional thin layer of a refractory metal (such as molybdenum or platinum) at a junction between the gate metal stack and a Schottky barrier layer. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby improving the long-term reliability of the devices. In addition, the '226 patent discusses a method for assessing the reliability of the HEMTs using elevated temperature life tests. Comprehensive direct current (DC) and radio frequency measurements are taken for discrete devices before and after the elevated temperature life test. In addition, before, during and after the high temperature life test, cross-sections of the HEMT are prepared using a focused ion beam (FIB). The cross-sections are studied by scanning transmission electron microscope using an energy dispersive X-ray for compositional and depth-profile (structural) analysis.
Park et al. in the article “Physical degradation of GaN HEMT devices under high drain bias reliability testing,” Microelectronics Reliability, vol. 49, pages 478-483, (2009) discusses AlGaN/GaN HEMTs that are epitaxially grown on semi-insulating SiC substrates. The reliability of the HEMTs is evaluated using an accelerated DC life test. In this test, the HEMT is subjected to elevated temperatures and variations in drain current and gate current are recorded during the tests. A focused ion beam is then used to lift out a cross-section from the HEMTs for studying the internal structural changes of the HEMT after the stress tests. Multiple cross-sections may be prepared from a single HEMT to study different regions of the HEMT. The structural changes in the HEMTs are observed by cross-sectional high resolution TEM (HRTEM) and high angle dark field imaging.
U.S. Pat. No. 7,538,718 (“the '718 patent”) discusses a failure detection procedure used for HEMTs. The procedure uses a control circuit to control a gate voltage switch for applying various gate voltages to an HEMT. The control circuit measures values of the drain current flow after the gate voltage is applied and thereby detects a failure of the transistor based on the current values. However, the '718 patent does not discuss observing the internal microstructure of the HEMT.
The HEMT reliability tests discussed above focus on either the surface morphology or internal structure of the HEMT via ex situ TEM. These tests do not properly correlate dislocation nucleation and cluster of point defects behaviors with electrical property degradation. One of the aspects of the present invention is an improved reliability test for HEMTs carried out by subjecting the HEMT to DC bias voltages and observing the microstructural changes in the HEMT by using in situ TEM. This reliability test may also be applicable to other devices with layered structures.